/**
 * @file    GT9881_CACHE.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#ifndef GT98XX_DEVICE_GT9881_CACHE_H_
#define GT98XX_DEVICE_GT9881_CACHE_H_

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"


/**
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */
/**
 * @struct  CacheTypedef
 * @brief   Cache Registers structure define
 */
typedef struct
{
  __IO uint32_t ENABLE;                 ///< Cache enable registers
  __IO uint32_t FLUSH;                  ///< Cache flush registers
  __IO uint32_t PERF_CNT_EN;            ///< Cache performance counter enable rigisters
  __IO uint32_t PERF_CNT_CLR;           ///< Cache preformance counter clear registers
       uint32_t RESERVED0[2];           ///< Reserved
  __IO uint32_t STATUS;                 ///< Cache enable status registers
  __IO uint32_t HIT_CNT;                ///< Cache hit count registers
  __IO uint32_t TRANS_CNT;              ///< Cache request count registers
}CacheTypedef;
/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define CACHE_BASE               (PERIPH_BASE + 0x3000UL)    ///< CACHE base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define CACHE                ((CACHE_TypeDef*)CACHE_BASE)      ///< CACHE operator
/** @} Peripheral_Declaration */


/**
 * @defgroup CACHE_Bitmap Cache Bitmap
 * @ingroup Peripheral_Registers_Bits_Definition
 * @brief Bitmap of Cache Registers
 * @{
 */

#define CACHE_ENABLE_Pos                (0U)    ///< Position of CACHE_ENABLE
#define CACHE_ENABLE_Msk                (0x1UL << CACHE_ENABLE_Pos)    ///< Bitmask of CACHE_ENABLE
/**
 * @def     CACHE_ENABLE
 * @brief   CACHE enable bit
 * <pre>
 * @a 1'b0 : Write 0 to disable CACHE.
 * @a 1'b1 : Write 1 to enable CACHE.
 * Default : 1'b0
 * </pre>
 */
#define CACHE_ENABLE                    CACHE_ENABLE_Msk

#define CACHE_FLUSH_Pos                 (0U)    ///< Position of CACHE_FLUSH
#define CACHE_FLUSH_Msk                 (0x1UL << CACHE_FLUSH_Pos)    ///< Bitmask of CACHE_FLUSH
/**
 * @def     CACHE_FLUSH
 * @brief   CACHE flush bit
 * <pre>
 * @a 1'b0 : N/A
 * @a 1'b1 : Write 1 to flush CACHE.
 * Default : 1'b0
 * </pre>
 */
#define CACHE_FLUSH                     CACHE_FLUSH_Msk

#define CACHE_PERF_CNT_EN_Pos           (0U)    ///< Position of CACHE_PERF_CNT_EN
#define CACHE_PERF_CNT_EN_Msk           (0x1UL << CACHE_PERF_CNT_EN_Pos)    ///< Bitmask of CACHE_PERF_CNT_EN
/**
 * @def     CACHE_PERF_CNT_EN
 * @brief   CACHE performance counter enable
 * <pre>
 * @a 1'h0 : Write 0 to disable CACHE performance counter
 * @a 1'h1 : Write 1 to enable CACHE performance counter
 * Default : 1'h0
 * </pre>
 */

#define CACHE_PERF_CNT_EN               CACHE_PERF_CNT_EN_Msk

#define CACHE_PERF_CNT_CLR_Pos          (0U)    ///< Position of CACHE_PERF_CNT_CLR
#define CACHE_PERF_CNT_CLR_Msk          (0x1UL << CACHE_PERF_CNT_CLR_Pos)    ///< Bitmask of CACHE_PERF_CNT_CLR
/**
 * @def     CACHE_PERF_CNT_CLR
 * @brief   CACHE performance counter clear
 * <pre>
 * @a 1'b0 : N/A
 * @a 1'b1 : Write 1 to clear CACHE performance counter.
 * Default : 1'b0
 * </pre>
 */
#define CACHE_PERF_CNT_CLR              CACHE_PERF_CNT_CLR_Msk

#define CACHE_STATUS_ENABLE_Pos         (0U)    ///< Position of CACHE_STATUS_ENABLE
#define CACHE_STATUS_ENABLE_Msk         (0x1UL << CACHE_STATUS_ENABLE_Pos)    ///< Bitmask of CACHE_STATUS_ENABLE
/**
 * @def     CACHE_STATUS_ENABLE
 * @brief   CACHE enable/bypass status
 * <pre>
 * @a 1'b0 : CACHE is enabled.
 * @a 1'b1 : CACHE is bypassed.
 * Default : 1'b0
 * </pre>
 */
#define CACHE_STATUS_ENABLE             CACHE_STATUS_ENABLE_Msk

#define CACHE_STATUS_FLUSH_Pos          (1U)    ///< Position of CACHE_STATUS_FLUSH
#define CACHE_STATUS_FLUSH_Msk          (0x1UL << CACHE_STATUS_FLUSH_Pos)    ///< Bitmask of CACHE_STATUS_FLUSH
/**
 * @def     CACHE_STATUS_FLUSH
 * @brief   CACHE flush status
 * <pre>
 * @a 1'b0 : CACHE is not flushed
 * @a 1'b1 : CACHE is flushed.
 * Default : 1'b0
 * </pre>
 */
#define CACHE_STATUS_FLUSH              CACHE_STATUS_FLUSH_Msk

#define CACHE_STATUS_CACHELINE_Pos      (2U)    ///< Position of CACHE_STATUS_CACHELINE
#define CACHE_STATUS_CACHELINE_Msk      (0x1UL << CACHE_STATUS_CACHELINE_Pos)    ///< Bitmask of CACHE_STATUS_CACHELINE
/**
 * @def     CACHE_STATUS_CACHELINE
 * @brief   Selected cachline status.
 * <pre>
 * @a 1'b0 : Selected cachelin is not flushed
 * @a 1'b1 : Selected cacheline is flushed.
 * Default : 1'b0
 * </pre>
 */
#define CACHE_STATUS_CACHELINE          CACHE_STATUS_CACHELINE_Msk

#define CACHE_HIT_CNT_Pos               (0U)    ///< Position of CACHE_HIT_CNT
#define CACHE_HIT_CNT_Msk               (0xFFFFFFFFUL << CACHE_HIT_CNT_Pos)    ///< Bitmask of CACHE_HIT_CNT
/**
 * @def     CACHE_HIT_CNT
 * @brief   Number of CACHE hit count.
 * <pre>
 * @a 1'b1 : Clear the register
 * Default : 1'b0
 * </pre>
 */
#define CACHE_HIT_CNT                   CACHE_HIT_CNT_Msk

#define CACHE_TRANS_CNT_Pos             (0U)    ///< Position of CACHE_TRANS_CNT
#define CACHE_TRANS_CNT_Msk             (0xFFFFFFFFUL << CACHE_TRANS_CNT_Pos)    ///< Bitmask of CACHE_TRANS_CNT
/**
 * @def     CACHE_TRANS_CNT
 * @brief   Number of CACHE request count
 * <pre>
 * @a 1'b1 : Clear the register
 * Default : 1'h0
 * </pre>
 */
#define CACHE_TRANS_CNT                 CACHE_TRANS_CNT_Msk

/** @} CACHE_Bitmap */

/**
 * @addtogroup Exported_Macros
 * @{
 */

/**
 * @def IS_CACHE_INSTANCE
 * @brief Check if INSTANCE is CACHE instance
 */
#define IS_CACHE_INSTANCE(INSTANCE)         ((INSTANCE) == CACHE)

/** @} Exported_Macros */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __GT9881_CACHE_H__ */

